1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices. More specifically, this invention relates to the manufacture of high performance semiconductor non-volatile memory devices. Even more specifically, this invention relates to the manufacture of high performance semiconductor non-volatile memory devices with reduced bit-line separation.
2. Discussion of the Related Art
In standard semiconductor manufacturing, the manufacture of non-volatile memory devices, Local Oxidation of Silicon (LOCOS) isolation or Shallow Trench Isolation (STI) has been commonly used to form the xe2x80x9cbit-linexe2x80x9d isolation. Later in the process flow, an anisotropic etch of the first layer of polysilicon provides the bit-line separation of the floating gates. Due to tight geometry, a critical resist mask is required to separate the first polysilicon layer above the isolation. This mask layer is very critical because it is required to print the smallest xe2x80x9cspacexe2x80x9d within the boundary of the isolation pillar. The term xe2x80x9cspacexe2x80x9d is defined as the open region in the imaging layer, the photoresist. The open region exposes the first layer of polysilicon and thus allows the transfer of the imaging layer onto the first layer of polysilicon to form the floating gate. Without the use of expensive lithographic illuminating source, new photoresist, and phase-shift mask to print the minimum feature, it is impossible to reduce the dimension of the spacing. The difficulty of forming this critical layer has been remedied by the increase in a dimension of the isolation pillar. This suggests that density has been compromised. Moreover, this ever-small feature size may outstrip the alignment envelope of the most advanced tool available.
Therefore, what is needed is a method to reduce the bit-line separation for non-volatile memory devices below the minimum printable dimension available from current photolithographic equipment.
According to the present invention, the foregoing and other objects and advantages are obtained by a method reducing features in a semiconductor device below the minimum printable dimension available from the photolithographic system in use.
In accordance with a first aspect of the invention, isolation structures are formed in a semiconductor substrate, a layer of tunnel oxide is formed on the surface of the semiconductor substrate between the isolation structures and a first layer of polysilicon forming a bitline is formed on the surface of the tunnel oxide. A layer of image sensitive photoresist is formed on the surface of the device, patterned and developed to form openings having a dimension of X1 in the layer of photoresist exposing portions of the underlying first layer of polysilicon. The layer of image sensitive photoresist is silylated, which causes the photoresist to swell thus causing the openings having a dimension of X1 to shrink to a dimension of X2.
In accordance with another aspect of the invention, the remaining layers of silylated and non-silylated photoresist are removed and the exposed portions of the first layer of polysilicon are anisotropically etched down to the surface of the underlying isolation structures. A conformal layer of ONO is formed on the surface of the device and a second layer of polysilicon is formed on the surface of the layer of ONO forming a wordline.
The described method thus provides a method of manufacturing a semiconductor device having reduced dimension bit-line isolation and reduces the effects of misalignment of the photoresist patterning mask.